Dr Chandan Karfa, Associate Professor, Dept of Computer Science and Engineering, IIT-G

Guwahati: Researchers at the Automation, Verification and Security Lab of Indian Institute of Technology-Guwahati (IIT-G) have developed secure and dependable integrated circuits (ICs) for faster and efficient computing.

The research looks at all aspects of the automated electronics design process such as synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country.

The findings have been published in top journals and conferences of the Institute of Electrical and Electronics Engineers (IEEE).

The research team is funded by ECR (Early Career Research), CRG (Core Research Grants) and Interdisciplinary Cyber-Physical Systems (ICPS) grants from the department of science and technology and by a research fellowship from Intel (India).

The paper has been authored by Dr Chandan Karfa, Associate Professor, Department of Computer Science and Engineering, IIT-G and co-authored by his research students, Mohammed Abderehman, D. Senapati, Surajit Das, Priyanka Panigrahi and Nilotpola Sarma.

The team has collaborated with various international experts.

Pointing out the importance and need of research in the area of increasing computational power, Dr Karfa said, “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualisation processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs. 

While multi core processors are being used in modern times, their computing power improvements continue to be insufficient. 

The IIT-G team emphasises on hardware acceleration specifications that are often written in high-level languages like in C/C++ and are converted to hardware code (or register transfer level or Register−Transfer Level (RTL code), in a process called High-Level Synthesis (HLS). 

Owing to the complex conversation process, HLS translation may introduce bugs in the design and therefore stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex. 

The team has developed simple and fast tools for HLS validation.

“We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators.  The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features,” Dr Karfa said.

In addition to these simulators, prototypes of which are available for testing, the IIT-G team has also developed a technology called HOST, which protects Integrated Circuits from IP theft during the design cycle.

The impact of the IIT Guwahati team’s work is enormous because of the increasing demand for hardware accelerators in disruptive areas such as Internet-of-Things (IoT), embedded and cyber-physical systems, machine learning and image processing applications.

“With the central government’s recent approval of a Rs 76,000-crore scheme to boost semiconductor manufacturing in the country, efficient EDA (electronic design automation) as designed by the research team will support and promote self-sufficiency in chip design,” a statement said.

Also read: Some sites for greenfield airport identified: Meghalaya govt tells HC

Trending Stories

Latest Stories

Leave a comment

Leave a comment